Open Source
ONNXim: A Fast, Cycle-level Multi-core NPU Simulator
https://github.com/PSAL-POSTECH/ONNXim
ONNXim is a fast cycle-level simulator that can model multi-core NPUs for DNN inference. Its features include the following:
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Faster simulation speed in comparison to other detailed NPU simulation frameworks (see the figure below).
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Support for modeling multi-core NPUs.
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Support for cycle-level simulation of memory (through Ramulator) and network-on-chip (through Booksim2), which is important for properly modeling memory-bound operations in deep learning.
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Use of ONNX graphs as DNN model specifications, enabling simulation of DNNs implemented in different deep learning frameworks (e.g., PyTorch and TensorFlow).
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Support language models that do not use ONNX graphs. Additionally, enable auto-regressive generation phases and iteration-level batching.
For more details, please refer to our paper below:
Hyungkyu Ham, Wonhyuk Yang, Yunseon Shin, Okkyun Woo, Guseul Heo, Sangyeop Lee, Jongse Park, Gwangsun Kim, "ONNXim: A Fast, Cycle-level Multi-core NPU Simulator," arXiv:2406.08051
Simulator for GPUs with Heterogeneous Memory Stack (HMS) [HPCA'24]
https://github.com/PSAL-POSTECH/accelsim_HMS
This repository contains the source code of our modified Accel-sim simulator used for our work below that proposed Heterogeneous Memory Stack (HMS):
Jeongmin Hong, Sungjun Cho, Geonwoo Park, Wonhyuk Yang, Young-Ho Gong and Gwangsun Kim, "Bandwidth-Effective DRAM Cache for GPU s with Storage-Class Memory," HPCA'24.